1. Field of the Invention
The present invention relates to a plasma display panel, and more particularly to a method and apparatus of driving a plasma display panel that is adaptive for improving its contrast and enabling its high speed driving.
2. Description of the Related Art
A plasma display panel (hereinafter ‘PDP’) excites a phosphorus by using ultraviolet ray to emit light, thereby displaying a picture, wherein the ultraviolet ray is generated when inert mixture gas such as He+Xe, Ne+Xe and He+Xe+Ne is discharged. The PDP has its picture quality improved in debt to recent technology development as well as being easy to be made thin in thickness and big in size
Referring to FIG. 1, a discharge cell of a three electrode AC surface discharge PDP of prior art includes scan electrodes Y1 to Yn, a sustain electrode Z, and address electrodes X1 to Xm crossing the scan electrodes Y1 to Yn and the sustain electrode Z perpendicularly.
A cell 1 is formed at each of the intersections of the scan electrodes Y1 to Y, the sustain electrode Z and the address electrodes X1 to Xm. The scan electrode Y1 to Yn and the sustain electrode Z are formed on an upper substrate (not shown). A dielectric layer and an MgO passivation layer is deposited on the upper substrate. The address electrodes X1 to Xm are formed on a lower substrate (not shown). Barrier ribs are formed on the lower substrate to prevent optical and electrical crosstalk from occurring between the cells that are horizontally adjacent to one another. A phosphorus layer is formed on the surface of the lower substrate and the barrier ribs, wherein the phosphorus is excited by vacuum ultraviolet to emit visible light. Inert mixture gas such as He+Xe, Ne+Xe and He+Xe+Ne is injected into a discharge space provided between the upper/lower substrates.
In order to realize the gray level of a picture, the PDP is time-dividedly driven by dividing one frame into several sub-fields that have the number of their light emission different from one another. Each sub field can be divided into a reset period to initialize a full screen, an address period to select scan lines and select cells from the selected scan lines, and a sustain period to realize gray levels in accordance with the number of discharge. For example, in the event of displaying a picture with 256 gray levels, the frame period (16.67 ms) corresponding to 1/60 second as in FIG. 2 is divided into 8 sub-fields (SF1 to SF8). Each of the 8 sub-fields (SF1 to SF8), as described above, is divided into the reset period, the address period and the sustain period. The reset period and the address period of each sub-field are the same for each sub-field, while the sustain period and the number of sustain pulses allotted thereto increase at the rate of 2n (n=0, 1, 2, 3, 4, 5, 6, 7) in each sub-field.
FIG. 3 illustrates a driving waveform of a PDP which is applied to two sub-fields.
Referring to FIG. 3, the PDP is driven in the manner of dividing one frame into a reset period to initialize a full screen, an address period to select cells and a sustain period to sustain the discharge of the selected cells.
In the beginning of the reset period, a rising ramp waveform Ramp-up is applied to all scan electrodes Y, and 0V is applied to the sustain electrode Z and the address electrode X. The rising ramp waveform Ramp-up causes a write dark discharge or a setup discharge to occur between the scan electrode Y and the address electrode X and the scan electrode Y and the sustain electrode Z within the cells of the Full screen, wherein almost no light is generated in the write dark discharge. The setup discharge causes positive wall charges to be accumulated in the address electrode X and the sustain electrode Z, and negative wall charges to be accumulated in the scan electrode Y.
In the end of the reset period, a falling ramp waveform Ramp-down is simultaneously applied to the scan electrodes Y, wherein the falling ramp waveform Ramp-down declines from around sustain voltage Vs. At the same time, sustain voltage Vs of positive polarity is applied to the sustain electrode Z, and 0V is applied to the address electrode X. When the falling ramp waveform Ramp-down is applied in this way, a erasure dark discharge or a set-down discharge is generated between the scan electrode Y and the sustain electrode Z, wherein almost no light is generated in the erasure dark discharge. The set-down discharge eliminates the excessive wall charges that are unnecessary for the address discharge.
In the address period, negative scan pulses SCAN are sequentially applied to the scan electrodes Y and at the same time positive data pulses DATA synchronized with the scan pulses SCAN are applied to the address electrodes X. When the voltage difference between the scan pulse SCAN and the data pulse DATA is added to the wall voltages generated in the reset period, the address discharge is generated within the cell to which the data pulse DATA is applied. When sustain voltages are applied, wall charges to the extent that the discharge might be generated are formed within the cells selected by the address discharge.
Positive DC voltage Zdc is applied to the sustain electrode Z for the set-down period and the address period so as not to generated a mis-discharge between the scan electrode Y and the sustain electrode Z.
In the sustain period, sustain pulses SUS are alternately applied to the scan electrodes Y and the sustain electrodes Z. In the cells selected by the address discharge, a sustain discharge, i.e., display discharge, is generated between the scan electrode Y and the sustain electrode Z whenever each sustain pulse SUS is applied as the wall voltage within the cell is added to the sustain pulse SUS.
Recently, the content or Xe tends to be increased in order to enhance discharge efficiency in the sealed discharge gas of the PDP. But, there is a problem that jitter value is heightened if the content of Xe is increased, wherein the jitter value represents the extent that discharge is delayed. If the discharge is delayed in this way, the discharge is generated in a big scale beyond the extent of a desired discharge level, so that it becomes difficult to control wall charges and the black brightness of the reset period heightens, thereby deteriorating its contrast characteristic. It will be explained in detail in conjunction with FIGS. 4 and 5.
In the PDP where the content of Xe is low, an applied voltage Vyz and a gap voltage Vg are supplied for the reset period, as shown in FIG. 4. The applied voltage is a voltage between the scan electrode Y and the sustain electrode Z, which is applied to the scan electrode Y and the sustain electrode Z from an external driving circuit, as shown in FIG. 3. The gap voltage Vg is a voltage applied to the discharge gas and the gap voltage Vg causes discharge to be generated within the cell.
If the content of Xe is low, the setup discharge of the reset period is generated when the gap voltage Vg reaches a firing voltage Vf. After the setup discharge is generated, the gap voltage Vg remains at the firing voltage Vf until the ramp waveform Ramp-dn of descending tilt is applied to the scan electrode Y. In the same manner, the set-down discharge of the reset period is generated when the gap voltage Vg reaches a firing voltage −Vf. After the set-down discharge is generated, the gap voltage Vg remains at the firing voltage −Vf until a scan bias voltage is applied to the scan electrode Y. On the other hand, in an initial state 41 before the reset period starts, the wall voltage Vg might be different by cells because the number of sustain discharges and so on are different by cells.
If the content of Xe is high, as shown in FIG. 5, the setup discharge is not generated at the point of time tf when the gap voltage Vg reaches the firing voltage Vf but is generated at the point of time tf′ that is delayed by a jitter value from the point of time tf because of the discharge delay caused by the high content of Xe. At the point of time tf′, the wall voltage Vf increases to a voltage higher than the firing voltage Vf as the external applied voltage Vyz increases. Accordingly, the setup discharge is generated in a big scale beyond the extent of a desired discharge level. Likewise, if the content of Xe is high, the set-down discharge is generated in a big scale.
Also, the PDP of prior art has the data pulse and the scan pulse wide in their pulse width because the PDP has the delay of address discharge relatively longer. Because of this, the PDP of prior art has a longer address period within the limited one frame period, thus there arises a problem that the sufficient sustain period cannot be secured when adding sub-fields to increase the resolution of the PDP or to improve picture quality.